Chennai

IP VERIFICATION ENGINEER

Verification Lead/Manager – Above 9 years experience Senior Verification – 2 to 8 years Job Description Experience in developing TB & TB components for block level and full chip level verification Experience in creating Test plan, writing Test cases Proficient in System Verilog\Verilog Proficient in writing Assertions UVM / OVM / VMM based Methodology with […]
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IP DESIGN ENGINEER

Job Description Experience in ASIC/FPGA IP development – Architecture, Microarchitecture. Able to Perform RTL coding, Debugging in simulation and hardware, LINT/CDC, DC Synthesis Proficient in Synthesizable and parameterized RTL coding using Verilog Language Experience with synthesis and static timing tools on ASIC/FPGA Experience in protocols such as PCI-Express, NVM Express, DDR, RapidIO is a plus […]
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