APSRAM Controller

Overview

Mobiveil’s APSRAM controller is a flexible, low-power, and low-latency solution designed for SRAM replacement in high-performance systems. Scalable from 64Mb to 1Gb, its multi-bank architecture enhances timing throughput, making it ideal for wearables, IoT devices, displays, automotive systems, industrial automation, and consumer electronics. Optimized for AI/ML, edge computing, and high-performance embedded systems, it supports seamless integration through its configurable AXI interface and adaptability across FPGA, Gate array, and Standard cell technologies. As part of Mobiveil’s Storage and Memory IP family, APSRAM reflects expertise in creating system-validated, low-risk IP solutions for compliance and interoperability.

  • Compliant with AXI4 and AP Memory specifications
  • Configurable address width, queue depth, and FIFO size
  • Supports self-refresh, auto-refresh, and power-down modes
  • Intelligent request scheduling for optimized performance
  • Maximizes bus efficiency with bank-level parallelism
  • Built-in support for asynchronous DRAM frequencies
  • Separate write and read queues with QoS control options
APSRAM Controller
Specifications
• Built-in asynchronous interface support for DRAM frequencies that are not equal to the AXI frequency • High, medium, normal, port priority • Separate write and read queues • The AXI ID signals support out-of-order transactions
Design Attributes
• Highly modular and configurable design • Layered architecture • Fully synchronous design • Supports both sync and async reset • Clearly demarked clock domains • Software control for key features
Product Package
• Configurable RTL Code • HDL-based test bench and behavioral models • Test cases • Protocol checkers, bus watchers, and performance monitors • Configurable synthesis scripts
Documentation
• Design Guide • Verification Guide • Synthesis Guide

Get the Detailed Product Brief here

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