PCIe Gen3 to SRIO Gen3 Bridge (FPGA)

Overview

Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems. Combining PCIe’s versatility with SRIO’s high-performance networking, this bridge supports full line-rate data transfer, making it ideal for defense, aerospace, medical imaging  telecommunications, and high-performance computing. It features advanced DMA and messaging engines for efficient data movement with minimal processor intervention, and its compact size and low power consumption make it suitable for embedded and industrial applications.

  • Mobiveil’s FPGA PCIe Gen5 Switch Solution with support for Intel and Xilinx FPGAs
  • Flexible single and multi-port configurations
  • Upstream (x16) and downstream (x8) lane scalability
  • Compatible with PCIe 5.0, backward compatible with PCIe 4.0, 3.1, 2.0, and 1.1
  • High link utilization, low latency, non-blocking architecture
  • Advanced error reporting and flow control logic
  • Link re-configuration and programmable link width support
  • Round Robin and Strict Priority arbitration with starvation detection
PCIe Gen5 Switch (FPGA)
Features
• PCIe Specification Compliance: Supports PCIe 5.0 (32 Gbps per lane) and is backward compatible with PCIe 4.0, 3.1, 2.0, and 1.1. • Scalable Configuration: Upstream support for x16 lanes and downstream support for x8 lanes. • Datapath Options: Configurable widths of 32, 64, 128, 256, or 512 bits. • Routing Configurations: Available in cut-through mode and SNF mode. • Compliance: Adheres to PCI-to-PCI Bridge Architecture Specification. • Error Reporting: Advanced error reporting for switch ports and embedded endpoints. • Power Management: Full PCI-PM and ASPM support for L0, L1, and L1 PM substate. • Arbitration: Round Robin and Strict Priority arbitration with starvation detection options.
Design Attributes
• Highly modular and programmable design • Fully synchronous design • Software control for key features
Product Package
• RTL Code • System Verilog/UVM based Testbench • Test cases • Protocol checkers and bus watchers
Documentation
• Design Guide • Verification Guide • Synthesis Guide

Get the Detailed Product Brief here

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