Mobiveil’s NVM Express Controller is highly flexible and configurable design targeted for both Enterprise and client class solutions that unlock the current and future potential of PCIe-based SSDs. The core efficiently supports multi-core architectures ensuring thread(s) may run on each core with their own queue and interrupt without any locks required. The controller architecture is carefully tailored to optimize link and throughput utilization, latency, reliability, power consumption, and silicon footprint. Mobiveil’s NVM Express controller can be used along with its PCI Express controller (GPEX) and any third party NAND Flash controller. 

  • Native NVMe Controller with proprietary control and Data path interfaces
  • NVMe Controller with AXI interface
  • UNH Certified
  • Highly Configurable
  • NVMe aware DMA Engine
  • Highly Efficient HW/SW Partitioning
  • NVMe Command Handler Firmware
  • Compliance to NVM Express 2.0 specification
  • Supports Multi-port Configuration for Multipath IO support
  • Support for configurable number of IO Queues
  • Support for configurable Queue depth
  • Support for Round Robin or Weighted Round Robin with Urgent Priority arbitration mechanism
  • Host memory page size support of 128MB
  • Efficient and streamlined command handling
  • Supports Fused Operations
  • Supports All Optional Admin Commands
  • Supports All Optional NVM Commands
  • Supports Multi-Path IO and Namespace Sharing capabilities
  • Supports Reservations
  • Supports multiple namespaces
  • Support for Zoned namespace command set and Key Value command set
  • E2E protection(16b / 32b / 64b) Support
  • Supports Copy command and Lock Command
  • Optional AXI interfaces for NVMe implementation in SoC
  • Well-defined Command Interface for local CPU to perform subsystem initialization and to handle all non-hardware
NVM Express block diagram
Configurable Options
• Multi-port or Single Port • Inclusion / Exclusion of AXI / Streaming interface modules • Number of IO Queues • IO Queue Depth • Number of DMA Engines • Number of Non-Volatile Memory Channels • Data Path Width (64, 128, 256, 512) • Data Buffer Size
Design Attributes
• Highly modular and configurable design • Layered architecture • Fully synchronous design • Supports both sync and async reset • Clearly demarked clock domains • Software control for key features • Multiple loopbacks for debug
Product Package
• RTL Code • UVM-based test bench and behavioral models • Test cases • Protocol checkers, bus watchers and performance monitors • Configurable synthesis shell • NVM Device FW Stack • FPGA Netlist for Prototype

Get the Detailed Product Brief here

Mobiveil’s OCTA PSRAM controller supports AP Memory’s Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of AP Memory’s Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.