• Supports low power EcoXiP family
    of devices from ADESTO
  • Supports OctaFlash devices from
  • Supports XccelaTM flash memory
    from MICRON
  • Limited or full support of other
    DDR-QUAD-SPI devices
  • Supports NOR Flash devices from Cypress (Infineon) including Semper family
  • Supports Winbond QSPI NAND Flash and similar devices
  • Winbond Octal NAND W35N04JWXXIC
  • Winbond NAND W25N01GWxxIG
  • Winbond NOR W25Q512JVxIQ
  • Adesto AT25XP032
  • Micron MT35XL256ABA
  • Micron MT25QU01GBBB8E0 (x4)
  • Macronix MX25UM51245G
  • Cypress HyperFlash S26KL512S
  • Cypress Semper S26HS01GT
  • Supports Cypress Hyperram S27KL0643
  • All similar devices in Market
  • Complaint to JESD251A Specification
  • Memory mapped access to the connected flash devices
  • Continuous Burst transfer support
  • Auto boot support
  • XIP support
  • AXI4 or AHB-Lite system interface for memory access with outstanding address support
  • AXI4 or APB interface port for CSR register access
  • Custom protocol Sequence based design to support an array of vendors
xspi flash controller block diagram
Design Attributes
• Highly modular and programmable design • Fully synchronous design • Software control for key features
Product Package
• RTL Code • System Verilog/UVM based Testbench • Test cases • Protocol checkers and bus watchers
• Design Guide • Verification Guide • Synthesis Guide

Get the Detailed Product Brief here

Mobiveil’s OCTA PSRAM controller supports AP Memory’s Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of AP Memory’s Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.