ONFI/Toggle IP

Overview

Mobiveil’s ONFI/Toggle IP is a highly flexible and configurable design targeted for enterprise storage applications like SSD. The ONFI/Toggle IP is used to access the external NAND flash for high speed transactions of multiple pages of read or write data taking advantage of the pipeline performance of newer enterprise NAND flash devices. The controller architecture allows control of most all ONFI 5.1 and toggle devices with flexible addressing schemes.
NAND Flash
  • Supports ONFI 5.1 all modes
  • Supports Toggle mode NAND interface
  • LDPC error correction available
  • Data path widths support of 16 bits to 256 bits PHY Data path width - 16 bit , 32bit
  • Supports ONFI 5.1 specification with NV-LPDDR4 mode of operation
  • Device independent RTL can work with any NAND device with just software reprogramming
  • Configurable Ready Busy Signal Configuration (Per device or Wired OR)
  • Supports volume addressing, suspend/resume functions, two pass programming, multi plane and asynchronous plane read commands
  • Supports User Interface to be Asynchronous with Flash Interface
  • Supports upto 256 LUNs per channel
  • Supports virtual LUNs feature to limit the gate count of EFC based on maximum possible simultaneous LUN operations in the end user system
  • Configurable warmup cycles through CSR register
  • DBI support
Enterprice Flash Controller block diagram Enterprice Flash Controller block diagram 2
NAND Flash Control Processor
• Create any kind of flash control sequences that are needed in your environment • Command can be created to be run in parallel with or without data and run in different LUN's or chip selects • Transaction based user interface • Software definable address scheme
Design Attributes
• Highly modular and configurable design • Fully synchronous design • Totally software configurable at runtime
Product Package
• Configurable RTL Code • HVL based test bench & Test cases • Design, Verification & Synthesis Guide • FPGA Netlist for Prototype • Synthesis Scripts • Documentation

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OCTA PSRAM
OCTA PSRAM
Mobiveil’s OCTA PSRAM controller supports AP Memory’s Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of AP Memory’s Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.
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