Mobiveil’s HyperBus flash Interface is a low pin count interface that achieves significantly higher performance than legacy parallel and SPI interfaces for SPI based NOR flashes. This controller Interface involves a simple read/write protocol that is suitable for both memories and peripheral interfaces. Interestingly, this interface only requires an additional six pins more than the QSPI. The HyperFlash memories coupled with our Hyperbus flash controller provide a new standard for performance by delivering upto 333 MB/s using this 12-pin interface.
- Compatible with Cypress/Spansion hyperbus based memory products
- 0 Wait State Write Burst Operation for HyperBus memory on AXI interface of up to 256 words
- True Continuous Burst Read operation for HyperFlash on HyperBus memory interface
- AXI-lite port for control registers accesses
- Minimum Gap between two Read Operations for highest performance on HyperBus memory interface
- Cache Line accesses for Execution-in-Place (XiP)
- HyperBus memory device clock of up to 166MHz. Up to 16 outstanding address support in AXI