Memory Controller

DDR4/3, LPDDR DDR5 AP Memory OCTA PSRAM Winbond HyperRAM AP Memory UHS PSRAM

Overview

Mobiveil’s UMMC (Universal Multi-port Memory Controller for RLDRAM2/3, DDR4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2) is a highly flexible and configurable design that supports RLDRAM2, RLDRAM3 and JEDEC compliant DDR4 3DS, DDR4, DDR3, LPDDR3, LPDDR3 and LPDDR2 memories. It is targeted for high bandwidth access and low power consumption such as next-generation mobile, networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.

Overview

Mobiveil’s UMMC (Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2) is a highly flexible and configurable design that supports RLDRAM2, RLDRAM3 and JEDEC compliant DDR5, DDR4 3DS, DDR4, DDR3, LPDDR3, LPDDR3 and LPDDR2 memories. It is targeted for high bandwidth access and low power consumption such as next-generation mobile, networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.

Overview

Mobiveil’s OCTA PSRAM controller supports AP Memory’s Xccela open-standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration of AP Memory’s Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give full flexibility for driving the memory control signals and timing adjustment for data sampling through various programmable control options. It is also tailor designed to support highly efficient continuous data transfer method to the memory corresponding to multiple consecutive system requests, resulting in high throughput.

Overview

Mobiveil’s HyperRAMTM controller supports Winbond’s HyperBus
based HyperRAMTM devices which are used in following applications:

  • IoT
  • Consumer devices
  • Automotive
  • Industrial

This controller enables smooth integration of Winbond’s HyperBus
HyperRAMTM memory chips into various new-gen SoCs’.
The controller is designed using Technology independent Verilog RTL and
supports all industry standard Simulator, Synthesis and Lint/CDC tools.

Overview

Most wearables devices typically monitor a finite set of
parameters which does not demand a lot of computing
power and memory size. Thus any wearable design
requires low power, lower RAM density and simplified
interface with optimal performances. These design
requirements make PSRAM a natural choice for wearable
applications.