IP VERIFICATION ENGINEER

Verification Lead/Manager – Above 9 years experience
Senior Verification – 2 to 8 years

Job Description

• Experience in developing TB & TB components for block level and full chip level verification
• Experience in creating Test plan, writing Test cases
• Proficient in System Verilog\Verilog
• Proficient in writing Assertions
• UVM / OVM / VMM based Methodology with strong understanding of OOPS concepts
• Good knowledge of Digital Fundamentals Good knowledge of Scripting (Perl, Shell), C language
• Familiar with different aspects of IP development: micro-architecture, RTL & TB implementation, Test plan, Functional coverage, Code coverage and regression
• Strong Simulation & Debugging skills
• Strong analytical skills with attention to detail
• Excellent written & verbal communications skills
• Knowledge of protocols such as PCI-Express, Rapid IO, NVM Express, NAND, CXL and DDR/ LPDDR
• Experience implementing directed and random test cases. Very good leadership skills.
• You will be a key player in IP development for Memory/Wired-Interconnect/ Networking/Mobile/ Video
• Develop BFMs, Drivers, Monitors and Scoreboard for the test bench in System Verilog.

Skills

Test Engineering WLAN WiFi