Job Archives
Job Description
- Knowledge of CPU microarchitectures
- Experience in deep submicron process technology nodes is strongly preferred
- Knowledge of library cells and optimizations from ARM, TSMC, and other high performance library vendors
- Solid understanding industry standard tools for FPGA and Emulation platforms
- FPGA and emulator flows and methodologies
- Verilog and SystemVerilog
- Emulator platforms (Cadence Palladium), platform bringup, digital design, verification, debugging, and waveform viewers
- Hardware emulators, such as Palladium, ZeBu, Veloce, or FPGA systems based on Xilinx or Altera FPGAs
- Vivado, Incisive/VCS, IXCOM, Design Compiler, Synplify, Verdi, or SimVision
- Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
- Debugging system-level software
- Programming skills in C and C++
- Scripting in Python, Tcl, or Perl
Skills
C C++ Perl Tcl Python
Job Features
Job Description Knowledge of CPU microarchitectures Experience in deep submicron process technology nodes is strongly preferred Knowledge of library cells and optimizations from ARM, TSMC, and other h...
Job Description
- Basics of SOC architecture, interconnect, and power management aspects
- Bring-up and validation on FPGA/emulation platforms and on new SOC designs
- Good knowledge of ARM Cortex-A7) / x86 / PowerPC CPU and memory system architecture
- Bare metal/Linux driver development experience. Experience in Firmware development, C language expertise for low level programming, Assembly language for any processor
- Good understanding on peripherals protocols(minimum 2): CIO, USB2.0/3.0/3.1, PCIe Gen1/2/3/4, Ethernet, SATA, SD/eMMC, NAND, SPI, I2C, UART.
- Should have good debug capabilities and hands on Board level debug experience and hands on using lab equipment - oscilloscopes, signal generators, protocol, and logic analyzers.
- Using JTAG based debuggers, compilers/linkers
Skills
SOC architecture interconnect
Job Features
Job Description Basics of SOC architecture, interconnect, and power management aspects Bring-up and validation on FPGA/emulation platforms and on new SOC designs Good knowledge of ARM Cortex-A7) / x86...
Job Description
- Good understanding of Verilog, SV and UVM concept.
- Hands on exp in writing UVM based testbench.
- Good debugging skills.
- Knowledge of AHB/AXI protocol.
- Worked on Assertion based verification.
- Should have knowledge of FIFO and command/response based verification
- Knowledge of cryptography/random number generator and security concept is advantage.
- Formal or jasper understanding.
- Worked on Verdi tool for debugging.
- Should have knowledge of Code and Functional coverage.
- Must have exp in handling some project and team.
- Knowledge of processor and silicon bringup.
Skills
AHB AXI jasper UVM Verilog
Job Features
Job Description Good understanding of Verilog, SV and UVM concept. Hands on exp in writing UVM based testbench. Good debugging skills. Knowledge of AHB/AXI protocol. Worked on Assertion based verifica...
Job Description
- Experience in ASIC synthesis
- Expertise in Synopsys/Cadence Synthesis tools
- Expertise with STA with prime time
- Good Experience in synthesis timing closure and interactions with DFT and PD.
- Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
- Experience in formal verification with Cadence LEC
- Expertise in ECO flows
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in RTL HDL languages Verilog/VHDL
- Understanding of RTL to GDS flow
- Expertise in Perl, TCL language
Skills
RTL HDL perl TCL ASIC
Job Features
Job Description Experience in ASIC synthesis Expertise in Synopsys/Cadence Synthesis tools Expertise with STA with prime time Good Experience in synthesis timing closure and interactions with DFT and ...
Job Description
- Place & Route tool experience on Cadence Innovus and/or Synopsys ICC2
- Timing closure experience in Synopsys PTSI
- Formal verification experience
- Physical verification experience
Skills
PTSI ICC2
Job Features
Job Description Place & Route tool experience on Cadence Innovus and/or Synopsys ICC2 Timing closure experience in Synopsys PTSI Formal verification experience Physical verification experience Ski...
Job Description
- In depth knowledge of DFT concepts
- In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
- In depth knowledge and hands on experience in MBIST insertion and Memory test validation
- Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
- Expertise in scripting languages such as perl, shell, etc.
- Experience in RTL and Gate level simulations of scan and MBIST test vectors
- Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)
- Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus
- Ability to work in an international team, dynamic environment
- Ability to learn and adapt to new tools and methodologies.
- Ability to do multi-tasking & work on several high priority designs in parallel.
- Excellent problem solving skills
- Excellent communication and team work skills and good English is required
Skills
ATPG DFT perl shell spyglass
Job Features
Job Description In depth knowledge of DFT concepts In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis In depth knowledge and...
Job Description
- Strong Embedded Software Developer Strong in C/C++
- Python skills will be good
- Knowledge in Artificial Intelligence and CNN will be plus Linux, Firmware and Device Driver development
- Ability to manage and build team Strong debugging skills Guide team technically Work with Marketing/Sales team in scaling business Teamwork
- Should have the ability to groom and build the team Identify potential skill development and upskill the team
- Should have strong software development skills Should define and improve the software process
- Should also be in a position to bring in Test Validation and Automation skills to the team Ability to scale the team to 100+ people
- Should be Business Savvy and customer-centric in approach
- Should have the ability to handle multiple projects, support technically Groom next level leaders that can enable scaling the team Linux and Firmware knowledge is crucial Good Program management skills Strong ownership
Skills
C/C++ Firmware and Device Driver development Linux Embedded Python
Job Features
Job Description Strong Embedded Software Developer Strong in C/C++ Python skills will be good Knowledge in Artificial Intelligence and CNN will be plus Linux, Firmware and Device Driver development Ab...
Job Description
- Candidate must have strong Marketing Skills
- Good Written and Oral communication
- Define Product Strategy by analyzing market requirements
- Identify New Market segments based on Emerging trends
- Perform Competitor Analysis
- Content creation for product marketing
- Experience in Semiconductor and System Market
- Experience in Digital Marketing, Social Media reach
Skills
Product Strategy Competitor Analysis Content Creation Social Media Marketing Management Oral Communication Product Marketing
Job Features
Job Description Candidate must have strong Marketing Skills Good Written and Oral communication Define Product Strategy by analyzing market requirements Identify New Market segments based on Emerging ...
Job Description
- Good knowledge in storage SSD or any storage devices )NAND Flash knowledge expertise
- Good at Python Programming is must
- NVMe basics
- PCIe basics
- Basic understanding on what is Firmware orwith firmware dev or Firmware validation test background
Skills
Storage Nvme SSD Firmware PCIe Nand Flash
Job Features
Job Description Good knowledge in storage SSD or any storage devices )NAND Flash knowledge expertise Good at Python Programming is must NVMe basics PCIe basics Basic understanding on what is Firmware ...
Job Description
- Experience in HDD, SSD, semiconductor, or non-volatile memory development
- Strong programming skills with experience in Python, C, or C++ programming.
- Experience with Agile development process Understanding of embedded programming. Ability to learn quickly and work independently.
- Exceptional written and verbal communication skills.
- Have a growth mindset and drive to continuously improve PCIe/NVMe protocol familiarity. Proficient in Microsoft Office applications Windows and Linux server storage environments
Skills
C++ C SSD HDD PCIe Python
Job Features
Job Description Experience in HDD, SSD, semiconductor, or non-volatile memory development Strong programming skills with experience in Python, C, or C++ programming. Experience with Agile development ...
Job Description
- IR Signoff for High Performance DSP Cores.
- Signal EM & Power EM Signoff for High Performance DSP Cores.
- Development of PG Grid spec for different DSP cores.
- ESD Signoff for High Performance DSP Cores.
- Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks
- Validating the IR Drops using Static IR , Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops.
- Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design.
- Good knowledge on PD would be helpful.
- Perl, TCL Scripting Skills.
- Good understanding on Power Integrity Signoff Checks
- Proficient in scripting languages (Tcl and Perl).
- Familiarity with Innovus for RDL / Bump Planning.
- Ability to communicate effectively with multiple global cross-functional teams.
Skills
PDN Redhawk RHSC Voltus at block level SOC
Job Features
Job Description IR Signoff for High Performance DSP Cores. Signal EM & Power EM Signoff for High Performance DSP Cores. Development of PG Grid spec for different DSP cores. ESD Signoff for High Pe...
Job Description
- Coming up with newer versions of on-chip transfer protocols aimed for high speed on hyperflex and eASIC architectures
- Developing new interconnect topologies to maximize data transfer throughput over long distances over FPGAs
- Extending support for AXI and other Industry Standard Memory Mapped and Streaming protocols
- Developing robust IP and networks which customers use in mission critical debug environments
- Developing microprocessor and microcontroller architectures optimized for implementation on Intel FPGAs
- Experience in technical leadership roles in Soft IP Design Solutions for ASIC/FPGA.
- Excellent verbal and written communication skills Working knowledge of hardware and software tools for content creation, execution and debug
- Strong attention to technical detail, data analysis and situational problem-solving skills
- Ability to handle complex issues with clarity to drive decisions Self-motivated and willing to take additional responsibilities for team's success Multitasking skills Collaborative, inclusive, influencer
Skills
hyperflex eASIC FPGA debug ASIC
Job Features
Job Description Coming up with newer versions of on-chip transfer protocols aimed for high speed on hyperflex and eASIC architectures Developing new interconnect topologies to maximize data transfer t...
Job Description
- Knowledge of CPU or switch architecture, logic and RTL design.
- Synthesis and speedpath debug, including false path and multi-cycle path analysis and power, area, and performance trade-offs.
- Experience optimizing RTL designs for high-speed timing and power.
- Solid understanding of Lint, CDC, Synthesis, DFT, verification, formal verification, and post-silicon debug.
- Experience with ASIC standard interfaces and memory system architecture
- Verification hands-on experience
- Backend flows hands-on experience.
- Architectural background
- Master's degree in Electrical Engineering.
Skills
CDC DFT RTL design Lint Synthesis
Job Features
Job Description Knowledge of CPU or switch architecture, logic and RTL design. Synthesis and speedpath debug, including false path and multi-cycle path analysis and power, area, and performance trade-...
Job Description
- Understanding the Bus/clock/power architecture
- Integrating of multiple sub-systems to Modem Top
- Running Synthesis/Lint/LEC/other Integrations flows
- Analyzing the overall system for optimizations
- Participating System-level analysis for Optimized structure
- Identifying the system level verification scenarios
- Debugging/Fixing the complex issues.
- Experience in PACDC, RDC is plus.
- Experience in RTL design & Integration of Base-band or any complex SOC architectures
- Experience in analyzing & debugging complex architectures
- Hands on system-level verification is Plus
- In-depth knowledge in Linting/Synthesis/Timing Analysis/LEC flows.
- Excellent analytical, Programming and debugging skills.
Skills
RTL design/integration System-level verification Timing-Analysis Lint LEC Flows
Job Features
Job Description Understanding the Bus/clock/power architecture Integrating of multiple sub-systems to Modem Top Running Synthesis/Lint/LEC/other Integrations flows Analyzing the overall system for opt...
Job Description
- Developing new methodologies in CDC/Lint checks etc
- Candidate should be well versed with RTL quality checks, Lint, CDC, RDC etc
- Candidate should be actively hands-on and well versed with scripting eg: PERL, Python and TCL.
- Candidate should be familiar with Verilog, System Verilog etc.
- Hands on experience with SpyGlass or VC-SpyGlass, scripting languages is must
- Candidate should be familiar with Verilog, System Verilog, VHDL etc.
- CAD/EDA tool/Flow development experience or design experience in the field of Lint, CDC is Must.
- Experience in PACDC, RDC is plus.
Skills
PACDC RDC VC-SpyGlas Lint
Job Features
Job Description Developing new methodologies in CDC/Lint checks etc Candidate should be well versed with RTL quality checks, Lint, CDC, RDC etc Candidate should be actively hands-on and well versed wi...
