STA ENGINEER

Job Description

• Experience in ASIC synthesis
• Expertise in Synopsys/Cadence Synthesis tools
• Expertise with STA with prime time
• Good Experience in synthesis timing closure and interactions with DFT and PD.
• Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
• Experience in formal verification with Cadence LEC
• Expertise in ECO flows
• Experience in Spyglass Lint/CDC checks and waiver creation
• Experience in RTL HDL languages Verilog/VHDL
• Understanding of RTL to GDS flow
• Expertise in Perl, TCL language

Skills

RTL HDL perl TCL ASIC