SOC INTEGRATION

Job Description

• Knowledge of CPU or switch architecture, logic and RTL design.
• Synthesis and speedpath debug, including false path and multi-cycle path analysis and power, area, and performance trade-offs.
• Experience optimizing RTL designs for high-speed timing and power.
• Solid understanding of Lint, CDC, Synthesis, DFT, verification, formal verification, and post-silicon debug.
• Experience with ASIC standard interfaces and memory system architecture
• Verification hands-on experience
• Backend flows hands-on experience.
• Architectural background
• Master’s degree in Electrical Engineering.

Skills

CDC DFT RTL design Lint Synthesis