Bangalore

POWER MANAGEMENT WITH REDHAWK

Job Description IR Signoff for High Performance DSP Cores. Signal EM & Power EM Signoff for High Performance DSP Cores. Development of PG Grid spec for different DSP cores. ESD Signoff for High Performance DSP Cores. Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks Validating the IR Drops using Static IR […]
Read More

FPGA VALIDATION

Job Description Coming up with newer versions of on-chip transfer protocols aimed for high speed on hyperflex and eASIC architectures Developing new interconnect topologies to maximize data transfer throughput over long distances over FPGAs Extending support for AXI and other Industry Standard Memory Mapped and Streaming protocols Developing robust IP and networks which customers use […]
Read More

SOC INTEGRATION

Job Description Knowledge of CPU or switch architecture, logic and RTL design. Synthesis and speedpath debug, including false path and multi-cycle path analysis and power, area, and performance trade-offs. Experience optimizing RTL designs for high-speed timing and power. Solid understanding of Lint, CDC, Synthesis, DFT, verification, formal verification, and post-silicon debug. Experience with ASIC standard […]
Read More

RTL/LTE

Job Description Understanding the Bus/clock/power architecture Integrating of multiple sub-systems to Modem Top Running Synthesis/Lint/LEC/other Integrations flows Analyzing the overall system for optimizations Participating System-level analysis for Optimized structure Identifying the system level verification scenarios Debugging/Fixing the complex issues. Experience in PACDC, RDC is plus. Experience in RTL design & Integration of Base-band or any […]
Read More

LINT/CDC – RTL Design

Job Description Developing new methodologies in CDC/Lint checks etc Candidate should be well versed with RTL quality checks, Lint, CDC, RDC etc Candidate should be actively hands-on and well versed with scripting eg: PERL, Python and TCL. Candidate should be familiar with Verilog, System Verilog etc. Hands on experience with SpyGlass or VC-SpyGlass, scripting languages […]
Read More

RTL IP DESIGN

Job Description Proven success in development of complex ASIC, FPGAs and products. Demonstrated capability to design major blocks involving ASIC, IPs, logic, and FPGAs. Excellent logic developer in Verilog / System Verilog. Aware of ASIC design flow. Experience with frontend design tools (Xcelium/Incisive, LINT tools, Genus/Design-Compiler, STA with Tempus/Primetime, power analysis); expert in at least […]
Read More

IP VERIFICATION ENGINEER

Verification Lead/Manager – Above 9 years experience Senior Verification – 2 to 8 years Job Description Experience in developing TB & TB components for block level and full chip level verification Experience in creating Test plan, writing Test cases Proficient in System Verilog\Verilog Proficient in writing Assertions UVM / OVM / VMM based Methodology with […]
Read More

IP DESIGN ENGINEER

Job Description Experience in ASIC/FPGA IP development – Architecture, Microarchitecture. Able to Perform RTL coding, Debugging in simulation and hardware, LINT/CDC, DC Synthesis Proficient in Synthesizable and parameterized RTL coding using Verilog Language Experience with synthesis and static timing tools on ASIC/FPGA Experience in protocols such as PCI-Express, NVM Express, DDR, RapidIO is a plus […]
Read More