5+ years

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EMULATION(Palladium)

Job Description Knowledge of CPU microarchitectures Experience in deep submicron process technology nodes is strongly preferred Knowledge of library cells and optimizations from ARM, TSMC, and other high performance library vendors Solid understanding industry standard tools for FPGA and Emulation platforms FPGA and emulator flows and methodologies Verilog and SystemVerilog Emulator platforms (Cadence Palladium), platform […]
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STA ENGINEER

Job Description Experience in ASIC synthesis Expertise in Synopsys/Cadence Synthesis tools Expertise with STA with prime time Good Experience in synthesis timing closure and interactions with DFT and PD. Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format) Experience in formal verification with Cadence LEC Expertise in ECO flows […]
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PHYSICAL DESIGN

Job Description Place & Route tool experience on Cadence Innovus and/or Synopsys ICC2 Timing closure experience in Synopsys PTSI Formal verification experience Physical verification experience Skills PTSI ICC2
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PRINCIPAL ENGINEER – FIRMWARE

Job Description Experience in HDD, SSD, semiconductor, or non-volatile memory development Strong programming skills with experience in Python, C, or C++ programming. Experience with Agile development process Understanding of embedded programming. Ability to learn quickly and work independently. Exceptional written and verbal communication skills. Have a growth mindset and drive to continuously improve PCIe/NVMe protocol […]
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POWER MANAGEMENT WITH REDHAWK

Job Description IR Signoff for High Performance DSP Cores. Signal EM & Power EM Signoff for High Performance DSP Cores. Development of PG Grid spec for different DSP cores. ESD Signoff for High Performance DSP Cores. Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks Validating the IR Drops using Static IR […]
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