3+ years

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Job Description Good understanding of Verilog, SV and UVM concept. Hands on exp in writing UVM based testbench. Good debugging skills. Knowledge of AHB/AXI protocol. Worked on Assertion based verification. Should have knowledge of FIFO and command/response based verification Knowledge of cryptography/random number generator and security concept is advantage. Formal or jasper understanding. Worked on […]
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Job Description Experience in ASIC/FPGA IP development – Architecture, Microarchitecture. Able to Perform RTL coding, Debugging in simulation and hardware, LINT/CDC, DC Synthesis Proficient in Synthesizable and parameterized RTL coding using Verilog Language Experience with synthesis and static timing tools on ASIC/FPGA Experience in protocols such as PCI-Express, NVM Express, DDR, RapidIO is a plus […]
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