RTA Selects Mobiveil,Inc to Develop New RapidIO Verification IP

Austin, TX (USA) – Jan 12, 2013 The golden simulation model currently used by the members of RapidIO Trade association is a C model that was originally developed almost a decade ago. Since its original development this model has been enhanced in multiple phases over the years to support the 1.3, 2.0, 2.1 and current 2.2 specifications. Over the last decade design verification methodologies have been evolving towards the use of system Verilog and a higher level, highly randomized and coverage driven verification process. The growing gap between the needs of RapidIO developers and the capabilities of the RapidIO bus functional model necessitated the development of a new bus functional model.

The new RapidIO bus functional model will be based on system Verilog and will support the standard Universal Verification Methodology (UVM). This model will support the soon to be ratified RapidIO 3.0 specification along with the prior versions of 2.x, and 1.3. The model provides a highly capable compliance verification solution for the RapidIO protocol. The avoid confusion with the current C-based BFM we are referring to this new model as the RapidIO verification IP (VIP). The RapidIO VIP can be easily combined with any other UVM compliant verification components to support a broader verification environment.

The RapidIO VIP is under development now and is planned to be available to RapidIO member companies, who are members of the BFM working group, in the summer of 2013. We invite BFM member companies to participate in the weekly BFM working group calls, scheduled for Thursday mornings. The BFM working group is responsible for developing the acceptance criteria for the model and for assisting in the verification of the model.

The RapidIO VIP uses a layered architecture that is divided in to Logical, Transport and Physical layers. An IO Link monitor handles protocol checking and is fully compliant to the Rapid IO specification. This monitor provides hooks for implementing functional coverage, scoreboard and checker functionality.

The RapidIO VIP also provides an extensive compliance test suite to verify all possible functional compliance scenarios. It simplifies the verification flow and reduces the verification effort. It can be used to verify standalone design IP, SoC and system level designs. Stimulus generation is fully automated and gives larger flexibility for the user to generate directed and random test scenarios. Users can constrain the randomization at different levels and functional coverage metrics help gauge the effectiveness of the randomization.
The RapidIO VIP models all of the registers in the RapidIO specification and provides coverage of these registers. Register model can be used to verify the properties of the registers and can also be used by the scoreboard, monitor and functional coverage models.

The RapidIO VIP is highly configurable and collects and reports functional coverage data. It provides a detailed report log on the packets and symbols. Multiple levels of verbosity are supported which makes debugging easier. It handles verbosity controllability for the different layers as well.

The RapidIO VIP can easily be integrated in to cycle-based or event-based simulation environments and supports latest version of major simulators in the industry.

Features Supported Include:

Supports RapidIO specification versions 3.0, 2.1, 2.0, and 1.3.
Supports 1x, 2x, 4x 8x and 16x lane configurations.
1.25 Gbaud, 2.5 Gbaud, 3.125 Gbaud, 5 Gbaud and 6.25 Gbaud lane rates.
Supports 66, 50 and 34-bit addressing on the RapidIO interface.
Supports all types of packet formats.
IDLE2 Sequence, Long Control Symbols and Data Scrambling.
Supports out of order transaction generation and handling.
Supports critical request flow (CRF)
Supports all transaction flows, with all priorities
Supports test pattern generation at all levels of protocol layers.
Supports error injection and error detection at all levels of protocol layers.
Provides Compliance Test Suite.
Functional Coverage.

About Mobiveil:
Mobiveil is a market leader in high speed peripheral interconnects, Memory and storage Silicon IP. With a solid roadmap for SRIO 3.0, PCI Express Gen3, DDR4 and NVM Express controller, and a team with over 15 years of IP delivery experience, Mobiveil offers high quality and fully configurable Soft IP cores that have been proven in commercial IC solutions with leading semiconductor customers.

Mobiveil is a member and an active participant in the RapidIO Trade Association (RTA) that drives the standard and specification for RapidIO bus protocol. Mobiveil recently announced the support for 10xN to its RapidIO portfolio, which further helps customers scale the port performance from 10Gbps to 160Gbps. To learn more about Mobiveil’s RapidIO offering please email (ip@mobiveil.com) or visit the website (http://mobiveil.com/) where you may download GRIO and RAB(RapidIO to AXI Bridge) product brochures.”

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