UFSHC Product

Overview

Universal Flash Storage (UFS) is a high-speed serial interface specification for flash storage. It is primarily for use in low power applications like smart phones and tablets. To achieve high performance and low power, UFS adopts MIPI specifications for the interconnect layer and PHY. It is based on MIPI UNIPRO and M-PHY specifications. UFS utilizes the SCSI command set supporting multiple command queuing and muti threaded programming. UFS Host Controller interface (UFSHCI) specification defines the data structures and programming model to interface host SW with UFS device.In Version 4.0, the HCI spec added Multi-Circular Queue (MCQ) definition to improve UFS storage performance. UFS supports advanced power management techniques, such as power gating, to minimize power consumption.

Mobiveil’s UFS Host Controller Implements UFS4.0 spec. This controller is designed to support both MCQ and legacy mode. The controller supports high performance by optimizing the latency involved in fetching the commands and data from host. Power efficiency is maintained by supporting various power savings states like hibernate and Sleep.

Device Supported:
  • Complaint to UFS4.0 spec
  • Implement all registers as mentioned in the UFSHCI 4.0 spec (except crypto)
  • Legacy mode
    • Supports 32 entries per descriptor list.
    • Supports 32 outstanding commands.
  • Multi Circular queue mode
    • Supports up to 16 submission and 16 completion queues in this version.
    • Supports 256 outstanding commands.
    • Supports Round robin and strict priority arbitration
  • Supports 8 entries per task management list.
  • Supports 16 outstanding RTT.
  • Handles all types of UPIU.
  • Supports UIC layer config and control through DME commands.
  • Supports optional CRC for read and write data payload.
  • Supports Event specific interrupt.
  • Supports AUTO HIBERNATE entry and exit through DME commands
  • Supports AUTO initialization of UFS link post enable from SW
  • Supports AXI4 interface as the system bus
UFSHC
Design Attributes
• Highly modular and programmable design • Latency optimized design for high speed data transfers • Software control for key features
Documentation
• Design Guide • Verification Guide • Synthesis Guide
Product Packages
• RTL Code • System Verilog/UVM based Testbench • Test cases
Licensing Option
• Single Design or Multi-project license (HDL Source Code)

Get the Detailed Product Brief here

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