AP Memory ApSRAMTM Controller

Overview

Mobiveil’s ApSRAM is a highly flexible, low power, low latency controller. It is targeted for SRAM replacement memory that is designed to be assembled closer to the processing unit, acting as eSRAM. The memory can be scaled from 64Mb to 2Gb, and its multi-bank architecture provides better timing throughput. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities. The ApSRAM controller finds application in a wide array of electronic systems, including wearables, IoT devices, displays, automotive systems, industrial automation, and consumer electronics. Its high bandwidth and memory densities make it particularly advantageous for AI/ML applications within SoC/MCU systems, as well as for advanced data processing, edge computing, and high-performance embedded systems. ApSRAM Controller is part of Mobiveil’s Memory controller family of IP solutions. The controller’s configurable and layered architecture is independent of application logic, implementation tools and most importantly the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible AXI System interface makes it easy to be integrated into wide range of applications. ApSRAM controller leverages Mobiveil’s years of experience in HyperTransport, PCI, PCle, RapidIO technologies and in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter-operability.
  • Built-in asynchronous interface support for DRAM frequencies that are not equal to the AXI frequency
  • High, medium, normal, port priority
  • Separate write and read queues
  • The AXI ID signals support out-of-order transactions
APSRAM Controller
Features
• Support multiple ranks • Support 8 or 4 banks • Configurable AXI address width • Support different AXI data widths along with an additional data width converter in the AXI slave logic of the controller • Configurable request queue depth • Configurable write and read data FIFO size • Configurable QoS through various arbitration schemes • Support self-refresh and partial array self-refresh • Supports auto-refresh and per-bank refresh • Support various power-down modes – precharge / deep power-down • Support scan and BIST engine integration for AP memory • Support intelligent request scheduling • Maximizes bus efficiency through look-ahead command processing and bank-level parallelism
Design Attributes
• Highly modular and configurable design • Layered architecture • Fully synchronous design • Supports both synchronous and asynchronous reset • Clearly demarcated clock domains • Software control for key features
Product Package
• Configurable RTL code • HDL-based test bench and behavioral models • Test cases • Protocol checkers, bus watchers, and performance monitors • Configurable synthesis scripts
Documentation
• Design guide • Verification guide • Synthesis guide

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