Error Correction
Interface IP
Memory Controller
Flash Storage
System On Chip
Error Correction
Wireless
Wired
Overview
Mobiveil’s 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance. It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding. The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient. The core includes an early iteration termination feature based on a concurrent parity check engine, enabling early exit during an iteration. Additionally, the maximum number of iterations can be set during runtime via a wire. The core also supports the accumulation of computed LLRs for failed previous transmissions when using HARQ, enhancing its overall functionality and efficiency in 5G applications.
Overview
Mobiveil’s 50G PON LDPC Encoder/Decoder offers industry-leading LDPC error
correction in a low-power, small-footprint, high-reliability solution. LDPC incorporates
this advanced technology to ensure reliable high-speed data transmission over optical
fiber.
50G PON operates at much higher data rates, making it more sensitive to noise,
dispersion, and optical impairments. LDPC provides powerful error correction to
maintain link performance.
