Jobs

Job Description

• Proven success in development of complex ASIC, FPGAs and products.
• Demonstrated capability to design major blocks involving ASIC, IPs, logic, and FPGAs.
• Excellent logic developer in Verilog / System Verilog.
• Aware of ASIC design flow. Experience with frontend design tools (Xcelium/Incisive, LINT tools, Genus/Design-Compiler, STA with Tempus/Primetime, power analysis); expert in at least one of these areas. Exposure to backend tools a plus.
• Relevant experience in some major IPs and protocols, such as SERDES, PCIe and DDR4, and ASIC IP integration in general. Expert in at least one such area.
• Understands DFT, BIST, other DFx methodologies.
• Great scripting skills (Python, Bash, etc.)
• Familiarity with verification methodologies and emulation or prototyping experience helpful.
• Excellent problem-solving and debug skills. Comfortable researching IP, firmware, compiler, and systems domains as needed.

Skills

RTL Design FPGA AXI Stream Matlab Video processing exposure

Job Description

• Experience in developing TB & TB components for block level and full chip level verification
• Experience in creating Test plan, writing Test cases
• Proficient in System Verilog\Verilog
• Proficient in writing Assertions
• UVM / OVM / VMM based Methodology with strong understanding of OOPS concepts
• Good knowledge of Digital Fundamentals Good knowledge of Scripting (Perl, Shell), C language
• Familiar with different aspects of IP development: micro-architecture, RTL & TB implementation, Test plan, Functional coverage, Code coverage and regression
• Strong Simulation & Debugging skills
• Strong analytical skills with attention to detail
• Excellent written & verbal communications skills
• Knowledge of protocols such as PCI-Express, Rapid IO, NVM Express, NAND, CXL and DDR/ LPDDR
• Experience implementing directed and random test cases. Very good leadership skills.
• You will be a key player in IP development for Memory/Wired-Interconnect/ Networking/Mobile/ Video
• Develop BFMs, Drivers, Monitors and Scoreboard for the test bench in System Verilog.

Skills

Test Engineering WLAN WiFi

Job Description

• Experience in ASIC/FPGA IP development - Architecture, Microarchitecture.
• Able to Perform RTL coding, Debugging in simulation and hardware, LINT/CDC, DC Synthesis
• Proficient in Synthesizable and parameterized RTL coding using Verilog Language
• Experience with synthesis and static timing tools on ASIC/FPGA
• Experience in protocols such as PCI-Express, NVM Express, DDR, RapidIO is a plus and preferred.
• Candidate should be Self Motivated, Proactive and should have attention to detail
• Should be able to clearly communicate with other teams/team members on a day-to-day basis

Skills

Test Engineering WLAN WiFi