Overview

Mobiveil’s CXL2.0-AgileTM Accelerator platform is a PCIe® Gen5 add-in card with latest Intel’s Agilex I series FPGA. It supports Mobiveil’s latest high performance CXL Controller IP (COMPEXTM) that is highly configurable for a number of High-Performance Applications, such as Accelerators, Artificial Intelligence and Machine Learning.

Block Diagram Specifications Benefits

Interface specifications
  • PCIe Gen5 x 16 at edge fingers
  • PCIe Gen5 x 8 at PCIe Edge Connector
  • Two PCIe Gen5 x 8 at CXL IO connector (CXL Host slot)
Memory specifications
  • Supports upto 64GB of DDR4 memory for FPGA Logic and Processor subsystem
Environmental specifications
  • Operating temperature : 0 deg C to 55deg C
  • StorageTemperature : -20deg C to +70deg C
  • Humidity : 10% to 90% non-condensing
  • Airflow 400LFM
Mechanical specifications
  • PCIe Full length, Full height form factor 312mm x 111mm
Power specifications
  • Typical power consumption : Less than 100WSupport for Auxiliary Power feed
FPGA
  • Intel Agilex I series
Controller
Mobiveil IPs (To be licensed separately)
  • CXL Controller (COMPEXTM) – cxl.io, cxl.mem, cxl.cache
  • PCIe Gen5/Gen4 Controller (GPEXTM)
  • DDR4 Controller (UMMCTM)
Standard compliance
  • PCIe Base specifications 5.0
  • CXL 1.1, CXL 2.0 (TBD)
  • CXL2.0-AgileTM is an ideal Platform to leverage the capabilities of Mobiveil’s COMPEXTM IP.
  • CXL2.0-AgileTM along with Mobiveil’s COMPEXTM IP maintains memory coherency between the devices, allowing resource sharing for higher performance, reduced software stack complexity and lower overall system cost.
  • Emerging data-processing applications in AI, media, image and language processing, encryption and others will benefit significantly from Mobiveil’s COMPEXTM IP.
  • COMPEXTM IP uses Mobiveil’s PCI-SIG® compliant GPEXTMcontroller and it supports CXL.io, CXL.mem and CXL.cache layers that are highly efficient and configurable for a low-latency coherent path.

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