3+ years
Bangalore, Chennai, Hyderabad/Secunderabad
Posted 8 months ago

Job Description

  • Experience in ASIC/FPGA IP development – Architecture, Microarchitecture.
  • Able to Perform RTL coding, Debugging in simulation and hardware, LINT/CDC, DC Synthesis
  • Proficient in Synthesizable and parameterized RTL coding using Verilog Language
  • Experience with synthesis and static timing tools on ASIC/FPGA
  • Experience in protocols such as PCI-Express, NVM Express, DDR, RapidIO is a plus and preferred.
  • Candidate should be Self Motivated, Proactive and should have attention to detail
  • Should be able to clearly communicate with other teams/team members on a day-to-day basis

Skills

Test Engineering WLAN WiFi

Job Features

Job Category

Software Development

Industry

Software

Functional Area

Software

Experience

Min 3+ years

Education

software

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