RapidIO Product

Overview

Mobiveil Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface on the system side. The Mobiveil Generic RapidIO Controller Solution can be used as a Host or device. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint. Mobiveil Generic RapidIO Controller design is fully synchronous and adheres to standard synthesis, test insertion and physical design practices. The solution allows licensees to easily migrate among COT, FPGA, Gate array, structured ASIC and Standard cell technologies. The IP with its flexible user logic interface can be easily integrated into a wide range of applications.
  • Compliant to RapidlO Specifications revision 4.0.
  • Compliant with RapidlO Error Management Extension specification, Revision 4.0.
  • Implements Logical, Transport and Physical layers functions.
  • Architected for high link utilization and low latency.
  • Efficient receive and transmit buffering scheme.
  • Implements receiver controlled flow control.
  • Provides Packet oriented user logic interface.
RapidlO Controller block diagram
Features
• Serial and Parallel Interfaces supported • 1x, 2x and 4x serial interface • 64/128/256-bit internal data path • PBUS interface for configuration register access • Up to 256 bytes data payload • Hardware error recovery • Exhaustive error reporting and handling • Pass-Through mode of operation for RIO packets up to 288 bytes • Accept all Mode of operation for fall over support • 34/50/66b addressing, 8/16/32b Device ID
Design Attributes
• Highly modular and configurable design • Layered architecture • Fully synchronous design • Supports both sync and async reset • Clearly demarked clock domains • Software control for key features • Multiple loop backs for debug
Product Package
• Configurable RTL Code • Test cases • HDL based test bench and behavioral models • Protocol checkers, bus watchers and performance monitors • Configurable synthesis shell
Configurable Options
• PIO, DMA, Message, Data streaming or mixed mode of operation • Parallel/Serial mode of operation • Bypass support
Documentation
• Design Guide • Verification Guide • Synthesis Guide

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